
PIC18FXX39
DS30485A-page 42
Preliminary
2002 Microchip Technology Inc.
TABLE 4-1:
SPECIAL FUNCTION REGISTER MAP
Address
Name
Address
Name
Address
Name
Address
Name
FFFh
TOSU
FDFh
INDF2(3)
FBFh
CCPR1H
F9Fh
IPR1
FFEh
TOSH
FDEh
POSTINC2(3)
FBEh
CCPR1L*
F9Eh
PIR1
FFDh
TOSL
FDDh
POSTDEC2(3)
FBDh
CCP1CON*
F9Dh
PIE1
FFCh
STKPTR
FDCh
PREINC2(3)
FBCh
CCPR2H
F9Ch
—
FFBh
PCLATU
FDBh
PLUSW2(3)
FBBh
CCPR2L*
F9Bh
—
FFAh
PCLATH
FDAh
FSR2H
FBAh
CCP2CON*
F9Ah
—
FF9h
PCL
FD9h
FSR2L
FB9h
—
F99h
—
FF8h
TBLPTRU
FD8h
STATUS
FB8h
—
F98h
—
FF7h
TBLPTRH
FD7h
TMR0H
FB7h
—
F97h
—
FF6h
TBLPTRL
FD6h
TMR0L
FB6h
—
F96h
TRISE(2)
FF5h
TABLAT
FD5h
T0CON
FB5h
—
F95h
TRISD(2)
FF4h
PRODH
FD4h
—
FB4h
—
F94h
TRISC(4)
FF3h
PRODL
FD3h
OSCCON*
FB3h
TMR3H
F93h
TRISB
FF2h
INTCON
FD2h
LVDCON
FB2h
TMR3L
F92h
TRISA
FF1h
INTCON2
FD1h
WDTCON
FB1h
T3CON
F91h
—
FF0h
INTCON3
FD0h
RCON
FB0h
—
F90h
—
FEFh
INDF0(3)
FCFh
TMR1H
FAFh
SPBRG
F8Fh
—
FEEh
POSTINC0(3)
FCEh
TMR1L
FAEh
RCREG
F8Eh
—
FEDh
POSTDEC0(3)
FCDh
T1CON
FADh
TXREG
F8Dh
LATE(2)
FECh
PREINC0(3)
FCCh
TMR2*
FACh
TXSTA
F8Ch
LATD(2)
FEBh
PLUSW0(3)
FCBh
PR2*
FABh
RCSTA
F8Bh
LATC(4)
FEAh
FSR0H
FCAh
T2CON*
FAAh
—
F8Ah
LATB
FE9h
FSR0L
FC9h
SSPBUF
FA9h
EEADR
F89h
LATA
FE8h
WREG
FC8h
SSPADD
FA8h
EEDATA
F88h
—
FE7h
INDF1(3)
FC7h
SSPSTAT
FA7h
EECON2
F87h
—
FE6h
POSTINC1(3)
FC6h
SSPCON1
FA6h
EECON1
F86h
—
FE5h
POSTDEC1(3)
FC5h
SSPCON2
FA5h
—
F85h
—
FE4h
PREINC1(3)
FC4h
ADRESH
FA4h
—
F84h
PORTE(2)
FE3h
PLUSW1(3)
FC3h
ADRESL
FA3h
—
F83h
PORTD(2)
FE2h
FSR1H
FC2h
ADCON0
FA2h
IPR2
F82h
PORTC(4)
FE1h
FSR1L
FC1h
ADCON1
FA1h
PIR2
F81h
PORTB
FE0h
BSR
FC0h
—
FA0h
PIE2
F80h
PORTA
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits
are reserved in PIC18FXX39 devices. Users should not alter the values of these bits.
Note 1: Unimplemented registers are read as ‘0’.
2: This register is not available on PIC18F2X39 devices.
3: This is not a physical register.
4: Bits 1 and 2 are reserved; users should not alter their values.